16位并行相关器的VHDL程序

一位LED显示的VHDL程序，挺简单的，买的开发板里面带的-An LED display of the VHDL program, quite simply, to buy development board inside the zone

ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助(ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners)

FPGA-based high-speed image acquisition system

control stepper motor by fpga card with vhdl program

Ethernet 10GE MAC 以太网10G的MAC Verilog代码实现(Ethernet 10GE MAC)

Verilog-RISC CPU

基于DDS和SOPC的谐波信号发射器，拥有可调节的频率，阶段和谐波比例的谐波信号发射器由本文所设计。(Based on DDS and SOPC harmonic signal transmitter, with adjustable frequency, phase and harmonic proportion of harmonic signal transmitter designed by this article.)

说明：  很好的免费学些 verilog教程 欢迎下载(Learn a good free download verilog tutorials welcome)

用verilog写的基于cpld的出租车计费器的源码，需要的参考一下-Use verilog to write a taxi based cpld billing device source code, need to refer to

FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性