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lvds_ctr_top
说明: 用verilog编写的LVDS接口驱动程序,采用IOSERDES技术实现,经过Spartan6 FPGA调试验证,有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)
- 2020-03-16 10:29:10下载
- 积分:1
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非常多的verilog实例,对于刚入门者比较有用
非常多的verilog实例,对于刚入门者比较有用-lot of verilog example, just beginners more useful
- 2022-03-17 16:05:10下载
- 积分:1
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FPGA控制AD逐点采集信号,并将AD转换后的数据串行发送出去。
FPGA控制AD逐点采集信号,并将AD转换后的数据串行发送出去。-FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.
- 2023-05-07 13:55:03下载
- 积分:1
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key_debounce-source-code
这是fpga按键消抖的源代码,在很多fpga按键实验中都可以用到,能够进行代码移植。(This is the source code of the FPGA buttons, in many FPGA key experiments can be used, and can carry out code.)
- 2015-10-31 10:19:03下载
- 积分:1
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05_key_test
fpga key test 入门 xilinx 黑金的板子(fpga key test xilinx)
- 2017-07-27 09:27:58下载
- 积分:1
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srio
fpga平台实现srio通信,以及srio端口寄存器设计。(FPGA platform to achieve sRIO communication, as well as sRIO port register design.)
- 2017-07-09 16:52:45下载
- 积分:1
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verilog 写的 “梁祝”乐曲演奏电路
verilog 写的 “梁祝”乐曲演奏电路-verilog wrote " The Butterfly Lovers" music concert circuit
- 2022-02-03 08:31:54下载
- 积分:1
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AskPsk
说明: ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)
- 2005-11-26 09:14:32下载
- 积分:1
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QPSK调制的载波频偏估计 LR_algorithm
QPSK调制的载波频偏估计,是一个可以调用的函数。接收端进行了一系列的处理。经典的L&R法(QPSK-carrier frequence offset estimation_ L&R)
- 2020-06-27 04:40:02下载
- 积分:1
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CPU的VHDL设计代码
应用背景VHDL ;CPU设计...................................................................................................................................................................................................................................................................................................................................................................关键技术VHDL ;CPU设计...................................................................................................................................
- 2022-05-20 23:07:58下载
- 积分:1