交通管理与控制系统

说明：  用verilog编写的LVDS接口驱动程序，采用IOSERDES技术实现，经过Spartan6 FPGA调试验证，有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)

非常多的verilog实例，对于刚入门者比较有用-lot of verilog example, just beginners more useful

FPGA控制AD逐点采集信号，并将AD转换后的数据串行发送出去。-FPGA to control the signal sampling point by point AD, AD conversion and serial data sent.

这是fpga按键消抖的源代码，在很多fpga按键实验中都可以用到，能够进行代码移植。(This is the source code of the FPGA buttons, in many FPGA key experiments can be used, and can carry out code.)

fpga key test 入门 xilinx 黑金的板子(fpga key test xilinx)

fpga平台实现srio通信，以及srio端口寄存器设计。(FPGA platform to achieve sRIO communication, as well as sRIO port register design.)

verilog 写的 “梁祝”乐曲演奏电路-verilog wrote " The Butterfly Lovers" music concert circuit

说明：  ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)

QPSK调制的载波频偏估计，是一个可以调用的函数。接收端进行了一系列的处理。经典的L&R法(QPSK-carrier frequence offset estimation_ L&R)

应用背景VHDL  ；CPU设计...................................................................................................................................................................................................................................................................................................................................................................关键技术VHDL  ；CPU设计...................................................................................................................................