交通管理与控制系统

为了便于计算结果在FPGA中后续的计算和ip核中的调用，本代码输入信号为普通浮点型数据，输出为32位表示的浮点型数据。

verilog ADPLL file with testbench.v

六层的电梯控制系统 用VHDL描述同时还附有系统仿真图形

vhdl,十进制加减计数器，输出计数序列信号-vhdl, decimal addition and subtraction counter, the output count sequence signal

本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.

文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.

一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using

基于FPGA的等精度数字频率计，包含FPGA和单片机通信程序，解释非常详细。经过调试成功。(FPGA-based Precision Digital frequency meter, including FPGA and MCU communication program, explained in great detail. After successful commissioning.)

pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)

数字逻辑与系统的关于所有的器件74LS的介绍，功能表(Digital Logic and System devices 74LS on the introduction of all the menu)