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说明：  matlab bpsk with rayleigh performance expirement

Altera DE2 开发板试验2 第1部分VHDL答案(Altera DE2 Lab2 part1 VHDL answer)

this come from alter ,you can look and find it on line about h263.

异步FIFO 输入: 16bit 输出:16bit 深度:256(Asynchronous FIFO Input: 16bit Output: 16bit Depth: 256)

AD采集模块,设计模块采集AD5270的输出数据(AD Collection module Design module to collect the output data of AD5270 )

Xilinx CPLD源代码，使用XC9500系列CPLD,驱动液晶-Xilinx CPLD source code, use the XC9500 series CPLD, LCD Driver

自己编写的红外解码子程序，但CPU资源占用较高，作教学示范用途。(prepared their infrared decoding routines, but higher occupancy CPU resources for teaching demonstration purposes.)

这份文献主要介绍了dsp builder 8.0的功能及使用手册，介绍了如何和matlab一起使用的步骤。(This literature focuses on the dsp builder 8.0 features and user manual describes how to matlab and used in conjunction with steps.)

KDP晶体二倍频与三倍频；基于耦合波方程组；已于实验结果校核 (Sum Frequency in KDP)

电子密码锁-Electronic Code Lock