开关、 灯、 和多路复用器-DE2-115

说明：  用CASE实现4选1数据选择器 很实用 运用VERILOG(Using CASE to achieve 4 election 1 Data Selector practical use Verilog)

HDB3码在matlab中的仿真，包括原始码、AMI码及HDB码的相关仿真图形(HDB simulink in matlab)

波形产生器：用VHDL编写的波形产生器程序-Waveform Generator: Using VHDL prepared waveform generator procedure

说明：  数字示波器实验，利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(In the experiment of digital oscilloscope, AD, DA and VGA are used to realize simple oscilloscope. DA peripheral transmits sine wave to AD peripheral. AD peripheral resolves into digital signal and sends data to VGA peripheral for display. The waveform, waveform frequency and peak value of DA peripheral can be seen on VGA.)

文档包括双线性插值算法和最近邻域算法的详细介绍，以及算法的相关计算。(Documentation includes bilinear interpolation algorithm and the nearest neighbor algorithm which is described in detail, as well as algorithms related calculations.)

16： 00 FFT VHDL源代码，xFFT16快速傅立叶变换（FFT）核心计算16点复数FFT。输入数据是16个复数值的向量，表示为16位2s补码-16位表示一个数据的实部和虚部。

design cpu 16 bits by verilog HDL.

说明：  Xilinx Licenses 2018

这是一个简单的定时器模块使用计数器

分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.