分别用分频比交错法及累加器分频法完成非整数分频器设计。...

ds1302时钟驱动程序，已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)

一个数字电路设计：六层电梯自动运行的VHDL程序(a digital circuit:sixlift design)

一个基于C51指令系统的简易uCOS示范程序,有完整的代码分析-A command system based on the C51 model uCOS summary procedures, have a complete code analysis

quartus 中，自己写的tcl，分配io的例子。-Quartus in their own writing tcl, distribution io example.

基于FPGA的电子密码锁设计与实现，语言是VHDL语言，有注释(FPGA-based design and implementation of electronic locks, language is VHDL language, annotated)

其中包括AD9226的原理图和应用程序，可以参考完成其他编程(Including AD9226 schematics and applications, you can refer to complete other programming)

步进电机控制程序，用vhdl实现。可实现电机的正反转控制-Stepper motor control program, using vhdl implementation. Positive inversion of motor control can be realized

verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga

动态获取CPU使用率源码 可以加到压力测试里(Dynamic access to CPU use the source code )

《可综合的Verilog语法》国外著名大学老师编写，对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.