在 VHDL 乒乓 P 楚方法之后写的定时器模块

这是一个基本的ARM7_Core 有基本功能 但不是太完善-This is a basic ARM7_Core has the basic functions, but not too perfect

这是一个vhdl代码的进位选择加法器及其工作100%。

通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.

说明：  该资料是用vhdl编写的按键消抖程序，按键消抖在使用按键的数字电路中非常重要，如果不对按键信号进行处理，有可能会出现大量错误的按键信号。文件key_xd.vhd是按键消抖程序，文件key_xd.vwf是仿真波形文件。该程序已经通过仿真测试，并且在电路板上调试通过，效果理想。(The information is written in the key consumer vhdl shaking procedures, key consumer shaking in digital circuits using the buttons is very important, if not key signal processing, there may be a lot of the wrong button signal. File key_xd.vhd is key consumer shake procedure is the simulation waveform file key_xd.vwf file. The program has been tested by simulation and debugging in circuit board by, the results are satisfactory.)

传感信号无线数字传输系统的设计与实现.kdh(err)

实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)

关于5-11APSK在高斯信道中的误码率分析仿真程序，对具体调制方式及解码方式都有详细的过程(About 5-11APSK in Gaussian channel bit error rate analysis simulation program, has a detailed specific modulation and decoding process)

Program to implement convolution of two signals.

一个很有用的vhdl实用教程，很适合初学者学习，介绍了vhdl的一些基本概念，还有一些经典的实例。-A useful practical VHDL Tutorial, it is suitable for beginners to learn, introduced some basic concepts of VHDL, there are some classic examples.

如何编写测试文件，，test bench的编写方法和是列，，总结的非常好的东西(how to code test bench in verilog)