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alu
说明: VHDL实现的算术逻辑计算单元(ALU),包括modersim测试文件,即仿真结果。(VHDL implementation of the arithmetic logic calculation unit (ALU), including modersim test file, the simulation results.)
- 2011-03-26 21:18:01下载
- 积分:1
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Cirrus Logic EP9302 原理图 ORCAD格式
Cirrus Logic EP9302 原理图 ORCAD格式-Cirrus Logic EP9302 schematic ORCAD format
- 2022-08-22 05:47:43下载
- 积分:1
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sdram_hr_hw_4port
这个是DE2上的SDRAM 四个端口的驱动代码,相当实用!(This is a four-port SDRAM on a DE2 driver code, very useful!)
- 2010-07-14 21:21:05下载
- 积分:1
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Asynchronous FIFO controller Verilog Design and Implementation
异步FIFO控制器的Verilog设计与实现-Asynchronous FIFO controller Verilog Design and Implementation
- 2022-08-14 15:39:50下载
- 积分:1
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dpll
用verilog编写的全数字锁相环,包括鉴相器,模K计数器,加减脉冲模块和分频模块,都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )
- 2014-04-22 08:36:53下载
- 积分:1
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LPM_ROM
可生成rom.初学者可以看看。很不错的。理解后生成rom很容易的。(LPM_ROM .It is good for VHDL new learner)
- 2009-09-18 10:17:53下载
- 积分:1
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ethernet_tri_mode_rtl.tar
以太网控制器verilog,含有mac,mii接口(Ethernet controller verilog, containing mac, mii interface)
- 2007-12-19 23:51:08下载
- 积分:1
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万能频率器,可以修改其中的参数,可是实现任意的分频!很方便!...
万能频率器,可以修改其中的参数,可是实现任意的分频!很方便!-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!
- 2022-01-26 04:43:16下载
- 积分:1
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PCPU设计代码
说明: RISC 5级流水线CPU,带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)
- 2020-06-24 04:00:01下载
- 积分:1
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ad7606
ADC7606的驱动代码,采用verilog实现(ADC7606 driver code, using Verilog to achieve)
- 2021-03-30 09:39:10下载
- 积分:1