16点FFT的VHDL源代码，快速傅里叶变换的xfft16（FFT）计算核心…

外部ADC采集数据，存为数组文件。通过程序读入，然后即可求出ADC的SNR、SINAD、THD、ENOB等。(External ADC data collection, stored as an array of documents. Read through the program, then the ADC SNR, SINAD, THD, ENOB can be calculated.)

本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。 (In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.)

median filter details

基于sopc ep2c5开发板的时间标记服务例程-Sopc ep2c5 development board based on the time-stamping services routines

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)

简单的apb i2s接口，verilog代码，包括rtl实现和testbench(apb i2s interface . coded by Verilog. including rtl and testbench)

这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)

xlinx sparten 3E实验板，实现时钟闹钟功能，闹钟播放电子音乐，时钟，闹钟通过LCD屏显示。自己写的，亲测可用。                                                                                                                    

synopse sv培训lab，是学习systemverilog非常好的资料，放心下载。(synopsis sv training lab)

迫零-串行干扰删除检测的程序，包括16QAM和QPSK(Zero forcing- Interference Cancellation detection procedures, including 16QAM and QPSK)