16点FFT的VHDL源代码，快速傅里叶变换的xfft16（FFT）计算核心…

40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )

motionjpeg的FPGA编码实现，有点老了，但是可以参考．有些东西和h.264是差不多的．-motionjpeg FPGA Coding, a bit old, but the reference. Some things and h.264 is roughly the same.

Generating a wider ALU from two small ones

这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)

verilogHDL语言编写，简单的FPGA脉冲程序，初学者必备。(verilogHDL language, a simple FPGA pulse program, beginners must.)

UC1608 24064驱动 COG LCD驱动程序(UC1608 24064)

这是一个计算机组成原理综合性实验：设计8位cpu。该cpu是8bit的代码，包含有4个寄存器，一个存储器，还有alu以及控制器。一共可以实现16条指令。(This is a computer composition principle of comprehensive experiment: Design 8 cpu. The cpu is 8bit code contains four registers, a memory, as well as alu and controllers. A total of 16 instructions can be achieved.)

说明：  AD9361资料文档及其寄存器配置参数文档(Ad9361 data and configuration parameter document)

vhdl,七段数码管驱动程序，完成数字显示功能-vhdl, seven-segment digital tube driver, complete the digital display

VHDL Design of BCD to 7-segment decoder using PROM