设计采用Verilog HDL 16位CPU。

motionjpeg的FPGA编码实现，有点老了，但是可以参考．有些东西和h.264是差不多的．-motionjpeg FPGA Coding, a bit old, but the reference. Some things and h.264 is roughly the same.

说明：  系统介绍了数字开发系统平台FPGA设计中的部分技巧 对于FPGA开发研究人员具有一定的指导和帮助意义(Systematic introduction of digital development platform FPGA design techniques for FPGA development of some of the researchers have some sense of guidance and help)

采用骏龙科技这个13.1新版本破解器.对于已经用了老版本破解器的网友，请把bin和bin64下的sys_cpt.dll删除，然后把sys_cpt.dll.bak名字改成sys_cpt.dll，也就是先恢复正版，然后用这个破解器破解。注意老的license文件也要删除，改用这个新版本破解器附带的license(Cytech Technology 13.1 using the new version of this cracker. Has been used for the old version cracker users, please sys_cpt.dll bin and bin64 under Delete, and then changed the name of the sys_cpt.dll.bak sys_cpt.dll, which is first restore genuine, then use this cracker to crack. Note that the old license file should be deleted in favor of this new version of the license that came with crack)

multiplexerwe 的 vhdl 程序可以写也像 thisits 非常简单的代码为 beginers 了解 4： 1 多路复用器

usb 和VGA接口FPGA程序，主控芯片为xilinx公司的SP3e系列的500E芯片，VHD语言编写，工程文件，可以直接用ISE打开

说明：  verilog 版本，Xilinx玩转USB3.0，LVDS接口(verilog version,Xilinxplay with USB3.0,LVDS)

说明：  杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。 (杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.)

i2c core : i2c master top

verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)

一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了-A 8x8 matrix keyboard VHDL files and have Changan and short keys of key points, namely, to achieve a total of 128 keys, scanning with the clock used on the list of 1ms