这是一个基于VHDL语言编程的电子琴源代码程序，希望可以帮到大家...

FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~

微分器：利用数字锁相环进行位同步信号提取的关键模块(Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules)

用VHDL语言仿真歌曲刘德华的《月老》 -Simulation using VHDL language songs Andy Lau

3x3中值滤波器的FPGA实现现(VERILOG)可直接使用。 (3x3 median filter FPGA implementation of the present (VERILOG) can be used directly.)

一个比较有参考价值的sram IP核，对SOPC感兴趣的人士有一定的指导意义！该程序是采用avalon总线，可以直接内嵌进SOPC Builder。-A comparison reference value has sram IP core, on the SOPC interested people have a certain guide! The procedure is used avalon bus, can be directly embedded into the SOPC Builder.

Vhdl Golden Reference Guide.pdf

研究信道噪声对M-ary QAM的影响，适合数字通讯从业者(Effect of channel noise on M-ary QAM in)

vhdl语言实现的频率发生器，可以产生不同的频率-A frequency generator wirriten by VHDL, which can generate different frequecies.

USB3.0开发板资料，采用CYUSB3.0(USB3.0 development board, using CYUSB3.0)

Programmable IIR Filter written in Verilog and its respective modules.