这是一个基于VHDL语言编程的电子琴源代码程序，希望可以帮到大家...

vhdl参考程序，供初学者参考使用-VHDL reference procedures, their use and reference for beginners

this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the main file included in the project.-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the main file included in the project.

一个任意整数分频程序,采用VHDL语言编写，编译通过-An arbitrary integer frequency procedure for the VHDL language, the compiler through

Vivado同步计数器VHDL设计 具有异步复位和同步预置数功能 同步计数器同步计数器同步计数器(The Vivado synchronous counter VHDL is designed with asynchronous reset and synchronous preset function, synchronous counter, synchronous counter and synchronous counter.)

图像处理的中值滤波器，使用verilog开发环境编程实现。(Verilog development environment programming median filter)

加法计数器的VHDL工程，程序，仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU

FPGA部分源代码，关于dsp48的应用，从一本很好的书上下的

该部分的主要功能是完成基于FPGA的polar码编码。(The main function of this part is to complete the FPGA-based polar code coding.)

全加器的VHDL程序实现及仿真-full adder VHDL simulation program and

本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.