这是一个基于VHDL语言编程的电子琴源代码程序，希望可以帮到大家...

《Verilog HDL 程序设计教程》7-"Verilog HDL Design Guide," 7

这是OFDM调制matlab的程序，中间详细描述了调制的过程，希望对大家有用。(This is the OFDM modulation matlab procedures, a detailed description of the intermediate modulation process, I hope useful.)

verilog2000更新部分，请对照前一个标准。加入了一些新的支持-verilog2000 update, a former control standards. The inclusion of some new support

说明：  电网协议信道解交织器设计FPGA实现，适用于PB16的宽带电力线载波通信(Grid protocol channel deinterleaver design FPGA implementation, suitable for PB16 broadband power line carrier communication)

s5pv-u-boot-2011.06之增加LCD显示功能(s5pv-u-boot-2011.06 Increase LCD display function)

FIR滤波器的verilog HDL代码示例，以16阶为例(Verilog HDL code for fir filter)

matlab code for JTAG cable checking

可以产生ASK FSK PSK 等调制信号。非常好用已经实现了所有功能。在硬件测试通过了(Can generate ASK FSK PSK modulated signals and so on. Is very easy to use all the features has been achieved. On the hardware test of the)

RS编码器的fpga实现，有TESTBench(RS encoder to achieve the fpga, and TESTBench)

listing program clock