这是一个基于VHDL语言编程的电子琴源代码程序，希望可以帮到大家...

说明：  A low pass filter module based on FPGA, easy to transplant

简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)

these is about code for dlx processor

AMBE2000的压缩数据输出输入的Verilog代码，实现了自回环（loopback）效果. 希望对学习verilog语言的同学有所帮助。(The Verilog code of AMBE2000. input and output of compressed data to achieve a self-loop (loopback) effect. hope to help the one who is studying the verilog language.)

驱动8*8点阵块显示汉字，可以自己根据要显示的内容随意更改，已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)

给FPGA程序，使之产生信号，驱动AD7606读取数据，并行模式。(give FPGA signal to read AD7606)

VHDL源码 VHDL源码 -VHDL source VHDL source VHDL source

uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )

浙江大学体系结构实验课代码，5级流水线实现旁路和停顿(5-stage pipeline to achieve realization of the bypass pipeline bypass pause 5 pause)

通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)