VHDL实现了IIS接口程序，在Quartus II 6.0上编译通过，在板子上可以读取IIS数据...

PCI vhdl for Fpga designer to design PCI IP

用fpga驱动lcd的原代码，是用vhdl语言实现的-drive lcd by fpga，the source program is written by vhdl

基于FPGA的利用rom进行查询的方式生成一个频率为10KHZ的sin信号，编译成功，并实现功能仿真。(Query based on the the FPGA use of rom generate a frequency of 10 kHz sin signal, compiled successfully and to achieve functional simulation.)

本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.

verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)

说明：  report for a report for a class

用Verilog代码实现的乒乓操作，用Verilog代码实现的乒乓操作(Verilog pingpong)

VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)

Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis

延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module