介绍了用vhdl描述的各种硬件电路的实现，基本包括各种常用的电路。...

74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)

在FPGA上实现CAN总线SPI接口通信，使用Verilog语言(Realize SPI interface communication of CAN bus on FPGA, using Verilog language)

LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL

实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

多进制数字频率调制(MFSK)系统VHDL程序-Multi-band digital frequency modulation (MFSK) system VHDL procedures

fir滤波器，Verilog语言写的，容易看懂-fir filter, Verilog language written in easy to understand

利用verilog驱动LCD1602 本实验是用LCD1602显示英文。（LCD带字库）(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))

基于matlab和vhdl的通信原理gmsk调制算法，主要包括GMSK相位路径的计算,GMSK眼图的仿真以验证相位计算的正确性,正余弦表的量化及bin文件的生成,以及用VHDL硬件语言所描述的基于EPM7128的地址逻辑.(Matlab and vhdl based on the principle gmsk Modulation of communication, including GMSK phase path calculation, GMSK eye diagrams of the simulation to verify the correctness of the phase calculation, is the cosine table generating quantitative and bin files, and using VHDL hardware description language logic based on the address of EPM7128.)

XVRWARE Library Xilinx Inc. The XVRWARE Synthesis library provides macros and synthesis examples for constructing TMR circuits in VHDL for the Virtex architecture

说明：  pc与fpga之间通过千兆以太网交换机实现网络通信(Network communication between PC and FPGA via Gigabit Ethernet switch)