SPI 主

如何用VHDL语言对时钟进行分频以达到计数目的(how to achive counting by VHDL Language)

一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。(This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.)

---------------------------------------------------------------------------

说明：  Laplace可以应用于图像的锐化，根据其原理，对于Laplace后的图像同样可以进行边缘检测。(Laplace can be applied to image sharpening. According to its principle, edge detection can also be performed for images after Laplace.)

Synopsys® Timing Constraints and Optimization User Guide

说明：  adrv9009的测试平台的测试脚本，适合新人参考(Adrv9009 test platform test script, suitable for new reference)

这份代码完成的功能是通过蜂鸣器播放《梁祝》这首曲子，当然可以自行更改代码，以播放其它的乐曲，所用的硬件描述语言是VHDL，代码有四部分构成，顶层模块、预分频模块（产生基频）、音乐表格和分频模块（产生所需的各音调）。

EEPROM 的verilog仿真模型（cat24cxx系列）(verilog simulition Model of EEPROM,include cat24cxx)

文利用直接数字频率合成器(DDS)与CPLD技术和单片机控制技术，研制和 设计了高分辨率、高稳定度的函数信号发生(Wen using direct digital frequency synthesizer (DDS) and CPLD technology and single-chip microcomputer control technology, development and Design of high resolution, high stability function of the signal )

altera 官方rs232例程 很详细很实用-official rs232 routines in great detail altera very practical