可以实现对任意波形分任意频，分频加减通过按键实现。

使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。使用的DDS芯片为AD9852，在QuartusII下编写。(Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.)

载波同步的verilog代码，是新手学习同步的最佳选择，值得推荐。(Verilog code carrier synchronization, synchronization is the best choice for novices to learn, it is worth recommending.)

buffer for in/out data.

AGC(自动增益放大) Verilog代码 设计可以参考(AGC (automatic gain control) can refer to the Verilog code design )

是基于FPGA的5620的数模转换芯片底层的应用程序，希望有用。(Is a digital-analog converter chip underlying the 5620 FPGA-based applications, and I hope useful.)

通过UART在FPGA数码管上显示经纬度坐标的代码(By UART displayed on FPGA digital latitude and longitude coordinates of the code)

说明：  VHDL实现的算术逻辑计算单元（ALU），包括modersim测试文件，即仿真结果。(VHDL implementation of the arithmetic logic calculation unit (ALU), including modersim test file, the simulation results.)

基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波(Based on the median filter VHDL source image processing, image filtering can be achieved)

半加器

一个模拟ISA界面的简易小程式，简单易懂-ISA interface, a simple simulation of a small program, easy-to-read