刚写的一个44键盘程序，调了好多天才调出来，给大家提供参考。...

verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。(Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.)

时钟输入：在每个时钟的正沿或负沿对数据进行处理 联合开发网 - pudn.com

实现BCD码的加法，用VHDL实现，是书籍上配套的-BCD ADDER，Using VHDL

16X2液晶显示屏的FPGA显示驱动设计。-16x2 LCD display driver design of the FPGA.

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

VHDL语言设计；功能描述：键盘扫描，不包含去抖电路-VHDL language design Function description: the keyboard scanning, does not contain a circuit debounced

用vhdl编写的主从式代码，会比较接近，它涉及i2c接口，主从式，每行都有注释，我建议如果你想对代码进行编辑就使用灵活的编辑器

Mano s cpu for Man s instructions

verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)

伽罗华域的乘法器的设计，使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)