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jiaotongdeng
交通灯控制系统VHDL源码,用VHDL语言、MAXPLUS2环境设计实现(VHDL core)
- 2009-03-05 20:01:07下载
- 积分:1
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i2c
说明: I2C完整代码,可综合,可仿真,已经过验证(I2C code can been syn and simulation ,veritify)
- 2021-02-26 13:11:46下载
- 积分:1
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VHDLshuzidianlushejijiaocheng
VHDL数字电路设计教程
乔庐峰等译 当当网销量领先(VHDL tutorial on digital circuit design: (Brazil) Pedroni (Pedroni, VA) were, Joe Lu Feng, M. Publisher: Electronic Industry Press Dangdang sales leader)
- 2010-08-07 10:37:05下载
- 积分:1
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a2013_TCAS_NB-LDPC_decoder
Design of a GF(64)-LDPC Decoder Based on the
EMS Algorithm
- 2016-06-17 18:04:14下载
- 积分:1
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mdct_latest.tar
mdct, it contains DOC,MATLAB,source,synthesis.
- 2009-12-11 14:15:39下载
- 积分:1
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SPI的verilog代码的可编程时钟
SPI Verilog code with programmable clock
- 2022-10-30 18:55:03下载
- 积分:1
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File name: ADC0809.vhd features: Based on the VHDL language, easy to control imp...
文件名:ADC0809.vhd功能:基于VHDL语言,实现对ADC0809简单控制说明:ADC0809没有内部时钟,需外接10KHz~1290Hz的时钟号,这里由FPGA的系统时钟(50MHz)经256分频得到clk1(195KHz)作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.
- 2023-07-04 18:20:03下载
- 积分:1
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同步FIFO功能,通过Modelsim仿真Verilog语言描述6…
同步FIFO功能,verilog语言描述,通过了modelsim 6.0 仿真,Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated
- 2022-03-24 20:37:31下载
- 积分:1
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主要是步进电机的驱动源,用Verilog VHDL开发,个人取向…
XC95144步进电机驱动器源码,采用verilog vhdl开发,个人原创-XC95144 stepper motor drive source, using verilog vhdl development, personal originality
- 2022-03-23 12:55:12下载
- 积分:1
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clock
EDA用maxplus2开发设计的简易数字钟,适合初学者,vhdL语言(EDA maxplus2 in development and design of simple digital clock, is suitable for beginners, vhdL language
)
- 2011-10-03 20:50:23下载
- 积分:1