扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

此程序基于ADC0809,它是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中。-Connection between ADC 0809, it was the eight CMOS A/D converters. Tablets containing eight analog switches, control eight of analog converters enter a Chinese.

这是一个用结构化语言编写的25抽头LMS算法建模.VHDL加法器/减法器、乘法器、延迟元件的代码分别编写并用LMS代码实例化。

verilog 入门概述 新手学习资料-Getting Started with an overview of novice learning materials verilog

用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program

Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.

用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错，然后将其纠错译码并输出，详细过程见仿真。(Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and then error correction decoding and output, see the detailed process simulation.)

1024点FFT快速傅立叶变换，包含说明文档和VHDL源代码，16位输入/输出，带DMA功能，xilinx的ip-1024-point FFT fast Fourier transform, and includes documentation, VHDL source code, 16 input/output, with DMA function, the ip xilinx

说明：  关于计时器 verilog语言，采用arm架构的m3，可以直接应用于soc(About timer verilog language, USES the arm architecture of m3, can be directly applied to soc)

二进制除法器，采用移位相减的方法实现，位数可调-The source code of a divider

CPLD下载线制作，内含电路图等，希望对大家有帮助-CPLD download line production, including circuit diagrams, etc., in the hope that we have to help