行人交通灯系统设计与7段显示

vhdl经典源代码――键盘接口设计，入门者必须掌握-vhdl classical source code-- the keyboard interface design, beginners must master

用VHDL语言将二进制数据转换成十进制数据，并将十进制的每一个位分离出来单独存放。使用状态机实现，程序简单，仿真效果很理想，占用可编程器件的资源较少。-VHDL language with the binary data into decimal data and decimal places separated from each store individually. Realize the use of state machine, the program is simple, simulation results are satisfactory, occupation of programmable devices have fewer resources.

基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行-fpga-baseed clock

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)

基于FPGA的电子密码锁的设计，内有Verilog HDL源码和各仿真图像-FPGA-based design of electronic locks, which have Verilog HDL source code and the simulation image

说明：  参照can芯片 saj1000控制器结构，写的can控制器(According to the structure of can chip saj1000 controller, the CAN controller is written)

本实例用于SDRAM完成读写功能: 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。(The examples for SDRAM read and write functions.)

一些简单的VHDL实例，主要是介绍一些基本逻辑们及一些组合、时序电路的例子，供大家参考-Some simple examples of VHDL, mainly to introduce some basic logic and some combination of sequential circuit examples for your reference

2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)

三八译码器，四位加法器，EDA实验，用verilog编写(EDA experiment with verilog language)