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FPGA的专业综合工具，学习此第三方工具的经典教程
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cputimer
基于 CPU 的精确计时器，时钟频率越高，计时越准(Based on the exact CPU timer, the higher clock frequency, the more time-quasi-)
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Verilog
32位存储器Verilog附带test文件，可以在modulesim仿真
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Altera Corporation for DE2 development board of the TV demonstration
用于Altera公司DE2开发板的TV demonstration-Altera Corporation for DE2 development board of the TV demonstration
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DCM_SP
数字时钟管理器，xilinx公司开发板集成时钟，实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)
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Implement the 7 segment diplay on spartan 3
Implement the 7 segment diplay on spartan 3
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用VHDL语言编程完成数码管0
用VHDL语言编程完成数码管0-255数字的显示-VHDL language programming with the 0-255 number to complete the display of the digital control
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30
说明： 30 bus for atp design
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Matlab-and-Modelsim
matlab怎么把数据输入到modelsim，文件读写的问题(data write and read from matlab to modelsim)
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lab4showTAs
4 seg display, button debouncer, and controller for parking meter
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