行人交通灯系统设计与7段显示

基于EDA技术设计4位十进制数字频率计的系统方案-Based on EDA technology design four decimal system solutions Cymometer

XVRWARE Library Xilinx Inc. The XVRWARE Synthesis library provides macros and synthesis examples for constructing TMR circuits in VHDL for the Virtex architecture

基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)

CH4CH2CH1VHDL 数字电路参考书所有程序8-CH4CH2CH1VHDL digital circuit reference all proceedings 8

vhdl very good debug release vhdl very good debug release

设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report

八阶巴特沃兹iir数字滤波器，四个二阶节，verilog代码实现，多路分时复用(batterworth，iir，8order，four second order section)

说明：  I2C完整代码，可综合，可仿真，已经过验证(I2C code can been syn and simulation ,veritify)

altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim 验证，文件中包含TESTBENCH ，直接可用-altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available

很好的fft学习程序感兴趣的同学可以看哈，下载一下。(it is very good )