vga显示代码,里面有ise工程文件,是直接调过去的,大家下载下来吧...

使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)

VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.

verilog实践 elc_clock 电子时钟设计(Verilog design practice elc_clock electronic clock)

vhdl语言，国外教材，数字信号处理算法(vhdl language, foreign materials, digital signal processing algorithms)

PCI总线仲裁参考设计，Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code

canbus verilog实现，原代码文件-canbus verilog implementation, the original source document

Xilinx 的DDR SDRAM控制器，用Verilog HDL描述- A DDR SDRAM contraller sample descripte in Verilog HDL ,base on Xilinx FPGA

ISE Design Suite Software Manuals and Help - PDF Collection,ISE 软件手册以及帮助。(ISE Design Suite Software Manuals and Help- PDF Collection, ISE software manuals as well as help.)

lgpl RS编解码 5-6 Reed-Solomon Codes-LGPL RS codec 5-6 Reed-Solomon Codes

前导零的计算 (Calculation of leading zeros)