介绍VHDL编程的资料，很详细，值得收藏

密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)

ADC0809 VHDL控制程序,基于VHDL语言，实现对ADC0809控制.-ADC0809 VHDL control procedures, based on the VHDL language, to achieve control of ADC0809.

图像降噪GUI界面，用到butterworth滤波器，中值滤波器和维纳滤波器，仅供参考。(noise reduction using media filter )

useful VHDL document for programmer

CPU代码-VHDL语言，实现了CPU的基本功能。-CPU code-VHDL language, the realization of the basic functions of the CPU.

说明：  秒表的实现，有暂停清零功能，Quartus II(Stopwatch realization, has the pause clear function)

四位十进制频率计的顶层控制模块，用于生成测频需要的复位及控制信号-four decimal frequency of top-level control modules, used to generate the required frequency measurement and control signals reset

实现FPGA接收429板卡发送的信号，并根据数据最后两位点亮相应的LED。(FPGA to achieve the 429 board to receive the signal sent, and according to the data of the last two of the corresponding LED.)

在altera的FPGA平台上实现rs232串口的自收发通信，速率为115200波特率，PC机使用串口调试助手即可观察结果。包含全部代码与工程，本人亲自测试通过。(Realization of self transmitting and receiving communication serial port of RS232 In altera on the FPGA platform, at a rate of 115200 baud rate, PC using serial debugging assistant can be observed. Contains all the code and engineering, I personally tested by. )

double edfe trigger d latch