一个UDP／IP核心架构的VHDL实现

2位并行加法器初学者必看初步了解FPGA-two count

bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

本源码为Nios II的开发示例,主要演示Nios II的I2C总线设计。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II I2C-bus design. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

doulos公司出的VHDL学习工具，非常易学易懂！~(doulos company out of the VHDL learning tool, very easy to understand! ~)

在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令(Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions)

说明：  关于quartus与modelsim 仿真(about quartus and modelsim simulator)

说明：  ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)

在Altera的FPGA开发板上运行第一个FPGA程序，以后我还会陆续发布这方面的代码-In Altera

说明：  本书纸版由机械工业出版社于2014年出版，张强编著，电子版由华章分社（北京华章图文信息有限公司）全球范围内制作与发行(The book was published in paperback by China machine press in 2014, and edited by zhang qiang. The electronic version was produced and distributed worldwide by huazhang branch (Beijing huazhang graphic information co., LTD.))

改VHDL代码可以实现超声波测距的功能，其精确度达到US级，可以用七段数码管显示其数值(sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging )