四分频的程序，输出clkout0就是二分频，clkout1是四分频

FPGA开发仿真工具modelsim的高级进阶教程，包括如何写脚本文件和后台批处理文件(FPGA Development Advanced simulation tools modelsim tutorial, including how to write a script file and back-office batch file)

说明：  Browser modularization processing, browser modularization combing, browser modularization expansion

实现了一个四层单电梯控制系统。门可以自动开关，也可以手动开关。代码可以集成，不超过驱动的现象。

QUARTUS 的配置及调试 flv的 -Quartus flv configuration and commissioning of the

misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

3. Distribution of this core must be free of charge. Charging is -- allowed only for value added services. Value added services -- would include copying fees, modifications, customizations, and -- inclusion in other products.-3. Distribution of this core must be free of charge. Charging is-- allowed only for value added services. Value added services-- would include copying fees, modifications, customizations, and-- inclusion in other products.

这个程序是 用于两个浮点数字加法器使用 VHDL 语言。

verilog基础练习，介绍怎样编写测试文件和仿真-Verilog based on exercises, how to introduce the preparation of test documentation and simulation

单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)

BCD码减法实现程序，非常完整，采用Verilog HDL语言实现。(BCD subtraction to achieve program code, very complete, using Verilog HDL language.)