中央空调的控制，3级控制系统，这个是中间控制的vhdl源代码

binary adder / subtracter in vhdl

vhdl学习基本编写程序，关于温度的读取和显示，vhdl学习基本编写程序，关于温度的读取和显示，vhdl学习基本编写程序，关于温度的读取和显示

基二8点fftverilog实现。经过modelsim仿真通过(Base 2 fftverilog implementation at 8 o clock. Go through the modelsim simulation)

VHDL经典设计，值得参考。压缩包里面文件直接用记事本打开即可。-VHDL design classic, it is also useful.

这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。(this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.)

基于verilog的FFT设计，使用vivado作为开发平台(Verilog based on the FFT design, the use of vivado as a development platform)

camping checklist for outback campers. A must for deep forest hikers.

Implementation of Serial Infrared decoder for low-speed IrDA communications.

ahb to apb master and slave