Viterbi译码器IP核，可以直接编译使用

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

crc5 bolck in usb contreoller

一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS )

数字跑表 该跑表具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s 按钮设置防抖-Digital stopwatch in the stopwatch with start, reset, suspend, suspended after the time and other functions can show the seconds counting time accurate to the second place after the decimal point, that can show**.** s Anti-Shake button settings

在Altera的FPGA开发板上运行第一个FPGA程序，以后我还会陆续发布这方面的代码-In Altera

通过总结当前对处理器架构的安全性能的处理方法，提出一种增强DSP处理器安全性能的方法。主要从并行性方面进行了改进。最后对改进的方法进行了仿真和结果分析。(By summing up the current security architecture of the processor performance approach, a DSP processor to enhance the safety performance of the method. Mainly from the aspects of parallelism to improve. Finally, improved methods and results of simulation analysis.)

rebuild file in check for

最近交互式电源技术，软交换、同步整流、频率固定(Alternating expressions Power technology recently、Softswitch, synchronous rectification, fixed frequency)

刚写的一个44键盘程序，调了好多天才调出来，给大家提供参考。-Just write a 44 keyboard program, tune out of tune a lot of talent to give you a reference.

非常好的EPM570(CPLD)学习程序源码,适合初学者,能让其快速入门(Very good EPM570 (CPLD) learning program source code, suitable for beginners, allowing its Quick Start)