Viterbi译码器IP核，可以直接编译使用

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，7-8章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 7- 8

图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)

TLC5510的驱动程序，采用Verilog语言编写(TLC5510 driver, the use of Verilog language)

rmii 以太网接口时序源代码，值得开发借鉴的哦(verilog hdl)

Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1(Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1)

9针的rs232与fpga之间的串口通信源程序(Rs232 9 pin serial communication with the source between fpga)

实现FPGA与PC通信的USB2.0接口,采用verilog语言实现(Implementation of FPGA and PC communication USB2.0 interface, using Verilog language to achieve)

基于Verilog 的电子日历与电子时钟程序，可以进行调日期、星期、时间的分钟与小时，通过几种模式来显示日历与时间。-Verilog-based electronic calendar and e-clock procedures, can be adjusted date, week, time of minutes and hours, through several models to display a calendar and time.

1024点fft verilog hdl-1024-point fft verilog hdl

说明：  altera ram ip教程。对RAM进行读写操作，写32个数据到RAM中，再将写入的32个数据从RAM中读出。(altera ram ip.write data to ram and read the data from the ram.)