VHDL源代码包

实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)

C51 verilog 源代码，可以在逻辑中实现51单片机功能-C51 verilog

实现pwm波的输出，按键可调占空比的，可通过连接pwm输出值led灯以检测占空比的变化(To realize the output of the PWM wave, key adjustable duty ratio, but through the connection PWM output value led lamp with testing duty ratio changes )

32位二进制除法器2

TCD1209D驱动程序 Verilog语言(TCD1209D driver Verilog language)

基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )

数码管显示有片选 模块 四输入，与其他模块相连即可使用-digital film of the election showed that four input modules, and other modules can be linked to the use of

关于LDPC解码的verilog程序，包含设计代码和验证环境(LDPC decoding on verilog procedures, including the design code and verification environment)

VHDL CODE FOR SQUARE WAVE GENERATOR

基于 verilog的卷积运算代码，应用于离散小波分析。(verilog conv)