VHDL源代码包

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10

quartusii 三分频电路，大家帮参考一下，有什么问题-one-third of quartusii frequency circuit, refer to U.S. help, have any problem

用VHDL实现的DDS逻辑，大家可以参考下-DDS achieved using VHDL logic, we can refer to the following

用Verilog实现1602的配置及功能。正确编译与实现(Realized by Verilog 1602 configurations and functions. Compilation and implementation of the right)

利用ANSYS有限元仿真软件对复合材料进行异常检测仿真实验，程序为一损伤样板模型(ANSYS finite element simulation software for composites simulation anomaly detection, the program is a damage model model)

NIOSII I2C接口模块及驱动程序，并含有测试程序。对想开发NIOS的工程师很有帮助(NIOSII I2C interface module and driver, and contains the test procedures. NIOS of engineers want to develop useful)

fsk调制与解调，此程序经过验证，可以运用，通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use

从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code

说明：  具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)

数字电子琴控制器的ＶＥＲＩＬＯＧ代码，含中文注释．-The number of organ controller Verilog code, with English Notes.