基于Verilog的PCI总线接口的设计及应用

随机数发生器

verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)

数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)

针对某船舶模型定位系统中调速电机，以FPGA(现场可编程门阵列)为控制器，采用数字比例积分调节器实现电机的速度控制算法，设计出数字化调速控制器(Positioning system for a ship model in the motor speed, the FPGA (field programmable gate array) for the controllers, proportional integral regulator with digital speed of the motor control algorithm, designed digital speed controller)

in this code very useful for designing real number concept

VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)

包括VHDL、verilog在内的各种设计实例，是学习硬件描述语言的帮手。共有82个实验例子，涉及各种语法规则。-82 VHDL, verilog test case, involving a variety of grammatical rules. which is you learn the HDL language helper.

等精度测试频率计，包括程序源代码以及相关注释-Precision test frequency meter, etc., including source code and related comments ......

两路十字路口的交通灯控制的VHDL源码，毕业设计，-Two-way traffic lights at the crossroads of the VHDL source code control, graduation design,

六十进制计数器，显示0到60.可以用数码管显示。(Six decimal counter 0-60 can use the digital display.)