sparc org, vhdl rtl code

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)

fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz

verilog 比较基础的教程 呵呵 新手学习学习啊 大家有资料工乡-basis of comparison of the tutorial Verilog Ha ha ah novice learn Rural U.S. Data Works

用verilog写的简单的CPU，有详细注释(Use verilog to write a simple CPU, with detailed notes)

ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)

用vhdl语言描写的存储器的读写，通俗易懂，简单实用。-Using VHDL language description of the memory read and write, user-friendly, simple and practical.

色彩空间转换硬件实现，用于图像处理，编码，解码部分-Color space conversion hardware for image processing, encoding, decoding part of the

这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)

This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery.

OFDM modulation source code written in Matlab