sparc org, vhdl rtl code

异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)

AD9910实现脉冲内线性调频信号，仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

CAN总线开发代码，FPGA与sja1000通信，可实现CAN的接收和发送。(The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.)

说明：  KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)

EV10AQ190A配置程序 EV10AQ190A configuration program(EV10AQ190A configuration program)

IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY

在FPGA中，采用verilog HDL语言实现图像处理算法sobel，仿真实验通过(In the FPGA using verilog HDL language image processing algorithms sobel, simulation experiment)

本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.

产生VGA彩条信号(Verilog 语言）-Generate VGA signal