sparc org, vhdl rtl code

protel中fpga封装库2，非常难找的-protel library 2 in fpga package, very difficult to find the

AD9850 VERILOG代码 硬件验证过，可以使用。

一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)

altera niosii SOPC helloword 学习-altera niosii SOPC helloword learning

SoC sample Code using Altera Xcaliber, good usefull SoC.

vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!-vhdl testbench preparation, textio the preparation is a difficult, but also a focus, and this is my collection of articles on textio the article, at the same time with a simple note!

FPGA 点亮数码管的灯，本例程支持6位数码管，因为我的FPGA开发板是这样子的(The lamp of digital tube illuminated by FPGA)

程序在报告中，要　用QuartusII运行，注意从word到运行环境中，可能有个别符号不兼容，重新在运行环境中输入那些符号就可以了-procedures in the report, with QuartusII operations, the attention to word from the operating environment, Some individual symbols are not compatible, the operating environment to re-enter those symbols on the

combinatorial modules

卷积码(2,1,7)编码器，一个输入，两个输出(Convolution code (2,1,7) encoder, an input and two outputs)