这个代码是Verilog HDL。

说明：  spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)

该程序实现多项式分数延迟（farrow）的设计。(The program polynomial fractional delay (farrow) design.)

基于vhdl编写的贪吃蛇游戏，课程设计必备(Based on the VHDL language of the snake game, curriculum design essential)

Browser modularization processing, browser modularization combing, browser modularization expansion

In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.

Verilog 最大公约数设计RTL级代码和芯片设计图(Verilog GCD Design and synthesis layout )

基于VHDL语言的波形发生器编程设计，能够实现常用波形的产生。(Waveform generator design based on VHDL programming, to achieve common waveform generated.)

控制路线和街道交叉口的简单程序，路线优先，街道上有车辆检测器；

调试bcm5396，写入和读取内部寄存器功能。功能验证可以用(Debug bcm5396, write and read the internal register function. Functional validation can be used)

LCD图形显示代码，已调试过，可以运行成功(LCD graphics display code has been debugged, you can run successfully)