Marquee with a program written in VHDL, and 60 binary counter program, one desig...

说明：  基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。(FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.)

通信系统的FSK调制程序，比较实用，包括完整的工程-FSK modulation communication system procedures, more practical, including the complete works

本例介绍直接合成带阻滤波器的方法，n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop coupled resonator elliptic filters is presented. Two different coupling schemes, which both include source–load coupling are used. The first coupling and routing scheme is the standard folded structure used in implementing bandpass elliptic filters with transmission zeros using resonators.)

FPGA-based high-speed image acquisition system

应用背景交通信号灯，自动检测有无行人，根据检测的状态来调节灯的状态，完整VHDL代码外加模拟仿真时序图关键技术 设计一个交通信号灯，有A、B两条路，装置自动检测A路口和B路口是否有人，RST信号能够将交通灯的状态置到A路绿灯亮，B路红灯亮，5秒钟检测一个状态，当A路口有人时，A路绿灯保持，每隔5秒检测一次，当A路口没有人了，绿灯变为黄灯，5S后再变为红灯，同时B路口变为绿灯，再5S后检测B是否有人，有人保持绿灯，没人变为黄灯，再变为红灯，依次进行~~

使用VHDL在CPLD上设计UART的一个项目-VHDL design UART

用verilog写的各种实用的分频器，很好的参考例子。-Using Verilog to write a variety of practical divider, a good reference example.

六十进制计数器，显示0到60.可以用数码管显示。(Six decimal counter 0-60 can use the digital display.)

延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module

flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench