在quartus软件下用VHDL语言实现DDS，可产生正弦，余弦，方波，三角波以及锯齿波。

说明：  SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

512阶高速FIR成型滤波器，四相位复用，树形加法和多级流水线结构。(512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.)

is61lv25616简单的verilog程序，完成sram读写 主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动(1lv25616 simple verilog program, complete sram read and w1lv25616 simple verilog program, complete sram read)

This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter

说明：  利用fpga实现gmsk的调制并仿真，全部代码(Fpga implements gmsk)

说明：  mojo v3 complete eagle schematic

用Verilog实现1602的配置及功能。正确编译与实现(Realized by Verilog 1602 configurations and functions. Compilation and implementation of the right)

此代码实现4人表决功能，4人中有三人同意即为通过。(Four voting)

Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency