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7 digital display decoder design 7 Digital is pure combinational circuits, usual...
7段数码显示译码器设计7段数码是纯组合电路,通常的小规模专用IC,如74或4000系列的器件只能作十进制BCD码译码,然而数字系统中的数据处理和运算都是二进制的,所以输出表达都是十六进制的,为了满足十六进制数的译码显示,最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器,输出信号LED7S的7位分别接数码管的7个段,高位在左,低位在右。例如当LED7S输出为“1101101”时,数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1;接有高电平的段发亮,于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
- 2022-08-11 21:55:01下载
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ssb
ssb的调制与解调,包括信号的产生、乘法器、加噪、BPF、解调等部分。(ssb modulation and demodulation, signal generation, multiplier, adding noise, BPF, demodulation section.)
- 2013-04-11 16:02:10下载
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VHDL程序讲解FIFO与RAM和ROM的数据交换
本资源详细的设计了一个FIFO的用法,将数据从ROM中读取送到FIFO缓存中然后RAM从FIFO缓存中读取数据存到内存中,改程序可以很好的学习三者之间的关系
- 2022-03-19 07:51:46下载
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此程序基于ADC0809,它是CMOS的8位A/D转换器,片内有8路模拟开关,可控制8个模拟量中的一个进入转换器中。...
此程序基于ADC0809,它是CMOS的8位A/D转换器,片内有8路模拟开关,可控制8个模拟量中的一个进入转换器中。-Connection between ADC 0809, it was the eight CMOS A/D converters. Tablets containing eight analog switches, control eight of analog converters enter a Chinese.
- 2023-07-11 04:50:03下载
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exp12
说明: 浙江大学计算机组成实验12指令扩展多周期CPU实现(The implementation of 12 instruction extended multi cycle CPU in Computer Composition Experiment of Zhejiang University)
- 2020-10-09 16:17:35下载
- 积分:1
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Using VHDL realize CPLD (EMP240T100C5) of the PWM output
利用VHDL实现CPLD(EMP240T100C5)的PWM输出-Using VHDL realize CPLD (EMP240T100C5) of the PWM output
- 2022-05-27 08:17:35下载
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Xilinx公司网站下的SDRAM Controller的参考设计,经过验证
Xilinx公司网站下的SDRAM Controller的参考设计,经过验证-Xilinx website of SDRAM Controller reference design, validated
- 2022-04-11 09:06:46下载
- 积分:1
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16C550-driver
C源碼16C550 串口驅動,使用中斷收送RS232資料(16C550 UART Driver)
- 2020-11-24 19:49:32下载
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useful VHDL document for programmer
useful VHDL document for programmer
- 2022-02-28 15:00:15下载
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4. If a modified source code is distributed, the original unmodified
4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.-4. If a modified source code is distributed, the original unmodified-- source code must also be included (or a link to the Free IP web-- site). In the modified source code there must be clear-- identification of the modified version.
- 2022-01-21 00:25:44下载
- 积分:1