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FPGA_Cordic_Atan_A
串行流水线格式:使用COrdic 算法计算反正切:向量模式下求角度 16bit :数据全部补码格式 (Serial line format: Use COrdic algorithm arctangent: seeking angle vector mode 16bit: full complement data format)
- 2014-10-13 20:55:52下载
- 积分:1
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具有桥式结构的传感器很多,如利用应变原理、磁电阻原理和其他变电阻原理的传感器,可以实现对压力、位移、加速度、磁场等物理量的测试。这种结构的差分输出可以增加灵敏度...
具有桥式结构的传感器很多,如利用应变原理、磁电阻原理和其他变电阻原理的传感器,可以实现对压力、位移、加速度、磁场等物理量的测试。这种结构的差分输出可以增加灵敏度,也有一定抵消外加干扰的能力。而且有的虽不是差分输出,比如电阻分压式的输出,可以认为是“半桥”,我们还可以人为的加上另一半,即加上一对精密电阻和一个电位器组成另一个分压电路,形成差分输出。每次调节电位器使差分输出为0,抵消零磁电压。-Bridge structure with many sensors, such as the use of contingency theory, the principle of magneto-resistance and other variable resistance sensor principle can be achieved on the pressure, displacement, acceleration, magnetic field, such as physical tests. The structure of the differential output can increase sensitivity, but also have some ability to offset the additional interference. And some is not a differential output, such as pressure resistance of the output type, you can think is
- 2023-08-23 20:55:03下载
- 积分:1
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just division the clock into 2
just division the clock into 2
- 2022-01-26 05:48:15下载
- 积分:1
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data_swith
verilog 代码实现串并转换,有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分:1
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RS
说明: 通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)
- 2013-07-18 16:09:22下载
- 积分:1
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用VHDL和verilog实现的四人抢答器
用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder
- 2023-07-17 00:15:04下载
- 积分:1
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Verilog HDL实现的I2C Slave模拟
Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave
- 2022-11-26 13:05:03下载
- 积分:1
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IC设计流程和设计方法
IC的设计可以分为两个部分,分别为:前端设计(也称逻辑设计)和后端设计(也称物理设计),这两个部分并没有统一严格的界限,凡涉及到与工艺有关的设计可称为后端设计。(The design of IC can be divided into two parts: front-end design (also called logic design) and back-end design (also known as physical design). These two parts do not have a uniform and strict boundary, and the design related to process can be called back-end design.)
- 2020-07-01 23:00:02下载
- 积分:1
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由VHDL 语言实现的数控分频
利用的是QUARTUES环境已经得到验证...
由VHDL 语言实现的数控分频
利用的是QUARTUES环境已经得到验证-By the NC VHDL language is the use of sub-frequency QUARTUES environment has been tested
- 2023-01-20 00:20:04下载
- 积分:1
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花了两周我们已经做出了一些改变,Altera DE1,DE2 PS2的IP
花了半个月才改好的Atera DE1/DE2 ps2 IP 驱动核。放在FPGA工程目录下可以直接使用。本IP能够驱动PS/2键盘和鼠标。使用时只要调用HAL目录下的文件即可以直接使用!-Spent a good two weeks we have made some changes Atera DE1/DE2 ps2 IP-driven nuclear. On the FPGA project directory can be used directly. The IP to drive PS/2 keyboard and mouse. When used as long as the call HAL directory file that can be used directly!
- 2023-07-13 20:25:03下载
- 积分:1