Verilog HDL语言的快速参考指南

密码锁 vhdl实现的密码锁 控制程序-mimasuo

ad9649的fpga驱动程序,FMC接口，基于Xilinx KC705(AD9649 Evaluation Board, FMC Interposer & Xilinx KC705 Reference Design)

高速多通道crc实现，可以并行实现5个通道数据的校验，支持10GB以太网标准-High-speed multi-channel crc implementation, can be achieved in parallel 5-channel data validation, support for 10GB Ethernet standard

并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。-And the string conversion module, which contains another one. Vhd file. One is its relatively simple to write the other is the reference.

PCIE仿真设计教程1-6，我帮大家收集到一起了(PCIE simulation design tutorial 1-6, I help you gather together.)

说明：  利用FPGA实现SDH开销中帧头A1A2的检测(FPGA implementation using SDH overhead in the frame header detection of A1A2)

基于NIOS驱动ALTERA DE1开发板的GPS模块工程-based on the nios ii drive the gpa module of altera de1 develop board,it s only a reference project

Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface

usb读取，仅供参考，在实际应用中要更改以下数据。(Read usb data)

基于DE2-115的数字时钟 1.液晶显示，数码管显示 2.整点报时 3.闹钟 4.设置时间 5.设置闹钟(Digital clock based on DE2-115 1. LCD display, digital tube display 2. whole point 3. alarm clock 4. setting time 5. set the alarm clock)