Building and Using Counters - DE2-115

说明：  i2c module，有i2c主机和从机模块(i2c module verilog VHDL base on i2c protocol)

简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)

FPGA代码，Designing_with_Quartus_II_Exercises_Ver11_v4_2.doc-FPGA code Designing_with_Quartus_II_Exercises_Ver1 1_v4_2.doc

fir滤波器，Verilog语言写的，容易看懂-fir filter, Verilog language written in easy to understand

4weimimasuo 可运行 可仿真 -aetgdffh tghj tjfgj fdg vbn t

8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn

说明：  MATLAB的SIMULINK和FPGA联合设计滤波器等，摆脱了传统的代码设计。(MATLAB's SIMULINK and FPGA jointly design filters and so on, and get rid of the traditional code design.)

4位电子密码锁，带键盘扫描、按键防抖动、LCD驱动编译码-four electronic password lock with a keyboard scan button shake, LCD driver encryption

频率计 测量范围1-100MHz 测量阈值0.1s 计数部分为FPGA/CPLD 语言VHDL 显示部分为51 单片机加八位数码管 语言C(Frequency meter Measuring range 1-100 MHZ Measure threshold is 0.1 s Count part of FPGA/CPLD Language VHDL Display part of 51 MCU with eight digital tube Language C)

quartus 中，自己写的tcl，分配io的例子。-Quartus in their own writing tcl, distribution io example.