Building and Using Counters - DE2-115

本程序实现数字钟系统，有整点报时功能，可显示切换年月日，定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)

带同步复位信号的二分频VHDL 程序-synchronous reset signal with the two-frequency VHDL procedures

重点介绍了双线性插值算法和该方法的Ｆ Ｐ ＧＡ硬件实现 方法， 包括图像数据缓冲单元、 插值系数生成单元以及插值计算单元等。(Highlights the bilinear interpolation algorithm and the method of F P GA hardware The method includes an image data buffer unit, the interpolation coefficient generating unit and an interpolation computing unit and the like.)

This rar files contains the presentation about FPGA and CPLD .

Hynix公司8M byte sdr sdram的verilog语言仿真实现。-Hynix company 8M byte sdr sdram realize the Verilog simulation language.

Electronic and system matlab simulation

基于VHDL语言的汉明码的译码，含有校正子跟纠错检错功能-Based on the VHDL language decoding Hamming Code, which contains sub-calibration error with error correction function

说明：  熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

这是我的VHDL格式的电子密码锁源程序，请站长审核啊-This is my VHDL source code format of the electronic lock, please review ah owners

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)