CH4CH2CH1VHDL 数字电路参考书所有程序9

Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim

说明：  快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流(Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.)

在fpga中对GPS信息采集程序。具有很好的参考性(In the fpga in the GPS information collection procedures. Has a very good reference)

matlab code for communication

lattice ECP3系列高速FPGA serdes测试代码(lattice ECP3 series high speed serdes test code)

verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)

基于fpga的位同步信号提取仿真 使用vhdl语言 quartus(To use vhdl language quartus fpga bit synchronization signal extraction-based simulation)

说明：  FIFO: First in, First out 代表先进的数据先出，后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO，根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)

基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming

用case 语句描述的4 选1 Mux 源码程序，好用(-4 with a case statement described 1 Mux source program, easy to use)