用vhdl语言编写的基于FPGA的波形发生器。对于做实验需要产生的波形非常有用。...

本代码绝对真实可靠，原用于长沙理工大学EDA课程设计之出租车计费器。本代码在要求的基础上添加显示时速和报警功能。希望此代码对有此需求的同学有所帮助！

Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be

以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)

说明：  基于labVIEW，控制电机等工作实例，程序基本完整(Based on labVIEW, control motor and other working cases, the program is basically complete)

QPSK在赖斯信道下的模拟仿真，包括K=6和K=10下的情况(QPSK in, Laisi Xin Road, under the simulation, including the case of K = 6 and K = 10 under)

说明：  通过spi实现加速度计adxl357读取xyz三轴方向的加速度值(Accelerometers adxl357 read the acceleration value of XYZ three-axis direction through SPI)

Ship navigation project

程序实现自动售货机的核心功能，设有3种价格的商品，可选择数量，有找钱功能。-program vending machine at the core function, with three kinds of commodity prices, the number of choice, having to function.

针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.)

在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分，顺序语句的执行方式十分类似于普通软件语言的程序执行方式，都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)