帧同步信号FPGA实现代码（可正常运行）

该文件用在CPLD上的，和C语言很接近，5位的计数器一个。-the documents on the CPLD, and the C language is close to that of the five counters one.

说明：  数字钟通过verilog实现，并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)

低频数字式相位测量仪 使用的VHDL语言，在MUXPLUS2环境下使用！ (digit hpase detecter use for low-frequence)

说明：  8通道24Bit同步A/D芯片AD7768的SPI接口例程(SPI interface routine of 8-channel 24bit synchronous A / D chip ad7768)

几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code

ldpc译码算法的matlab实现，码长960，码率1/2,完全模拟fpga硬件实现语言，量化处理。(ldpc decoding using matalb,code length 960,code rate 1/2)

关于FPGA排序算法的研究文献，有全排序和一些归并算法的文献介绍。(FPGA sequencing algorithm on the literature, there are some sort of sorting algorithm and the literature on the merger.)

利用最新的嵌入式开发工具EDK，在FPGA 中完成对PDIUSBD12 的硬件定制和固件编程，从而在FPGA 中实现U S B 控制器， 并最终完成U S B 的枚举过程、驱动程序的开发和简单的应用。(Using the latest embedded development tools, EDK, in the FPGA completes its PDIUSBD12 custom hardware and firmware programming, in order to realize USB controller in the FPGA, and ultimately complete the USB enumeration process of driver development and simple应用.)

说明：  Convolutional neural network code for fpga

用blockram实现移位寄存器，开发语言为verilog hdl(Shift register with blockram achieve the development language for the verilog hdl)