DDR（双速率）SDRAM控制器参考设计，xilinx提供

用Hspice实现一个三输入异或门，并分析其功耗和延时。(A three input XOR gate is implemented by Hspice, and its power consumption and delay are analyzed.)

这是一个LCD1602底层驱动代码，TI公司LM3S系列的(This is a LCD1602 underlying driver code, TI company LM3S series)

说明：  使用Verilog HDL ，FM调制信号。(Using Verilog, HDL, and FM modulation signals.)

4X4keypad的防抖动模块，用于假按键的检测-4X4keypad shake the module, the keys for false detection

FPGA核心代码，可在工程中直接使用。-FPGA core code, can be directly used in engineering.

2004 SNUG of systemverilog

基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM

能够在EDA环境下实现四位十进制数字密码锁的设置与开锁功能，并能更改使用密码，还可以防止抖动(EDA environment to achieve four decimal code lock and unlock function of the settings and change the use of passwords, but also to prevent the jitter)

高级FPGA设计__结构、实现和优化,中文翻译版(Advanced FPGA Design- Architecture, Implementation, and Optimization)

说明：  Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.