合众大公司XILINX_V4实验箱原理图

本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.

说明：  浮点数加法器的源代码,实现浮点数的加法功能，浮点数遵循的是IEEE745标准(floating_piont addition)

说明：  OFDM信号的发送与接收 ，需要自取。时域图，模糊图，削峰。(Sending and receiving of OFDM signal)

十分基础的CCD的测试程序，大家可以下载调试CCD(this is a ccd test chengxu ,it is very good to use ,you can down it )

说明：  用FPGA完成256*8的存储器的读写操作( complete reading and writing 256* 8 memory with FPGA )

数字时钟的VHDL语言描述，具有高精度，控制性能良好-Digital Clock description of the VHDL language, with high precision and good control performance

Xilinx Sysgen User Guide

vhdl编程语言电子书，英文的，有很多例子(VHDL programming language e-books, in English, there are many examples of)

利用FPGA实现SDRAM的读写操作，通过硬件测试。(FPGA implementation using SDRAM to read and write operation, hardware testing.)

用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)