VHDL开发环境，出租车计费系统，实现起步10元，每增加一公里，自动上涨2元。...

该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐 (The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)

无线通信调制解调用的verlog和matlab程序，很大很实用。(Wireless modem calls verlog and matlab program, very very practical.)

verilog code for 8 bit alu

基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)

说明：  基于quartusII的QDPSK调制解调vhdl程序。(Modulation and demodulation based quartusII of QDPSK vhdl program.)

基于verilog hdl编写的FPGA正弦信号发生器，已测试。(FPGA sine signal generator)

线性伸展TDC的verilog，包含门级网表(TDC linear stretch of verilog, includes gate-level netlist)

基于VHDL语言的并串转换程序，有四位的并行输出转换为串行输出-Based on the VHDL language and string conversion process, there are four parallel output is converted to serial output

地铁售票系统，基于VHDL，可实现站点设置，站点选择，选择购票数量，找零等一系列功能。-Metro ticketing system, based on VHDL, allows site settings, site selection, choose the number of tickets, Keep the change and a series of functions.

这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列-This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence