VHDL开发环境，出租车计费系统，实现起步10元，每增加一公里，自动上涨2元。...

FPGA入门系列实验教程——实验四.LED跑马灯(Getting Started with FPGA tutorial series of experiments- Experiment IV. LED Marquee)

DDS VHDL include everything of dds AD9914

这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.-This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.

uart_tr 异步串口通信主机 使用verilog HDL语言编写(uart_tr the host of the uart )

该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块-the source for several sine ROM, has been compiled and passed, can be directly downloaded, not internal ROM containing sine table, the Acer ROM module

一篇关于多相滤波器的论文,讲解了关于多信道的实现与仿真。(A paper about the polyphase filter，explained about the realization of multi-channel and simulation )

利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发 时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count )

说明：  数电实验FPGA verilog代码，包括秒表、全加器、半加器等。(FPGA Verilog code for digital experiment)

说明：  基于fpga的verilog实现ad及uart，并进行仿真验证(Verilog based on FPGA implements AD and uart, and carries out simulation verification)

gaisler公司在2011年发布的的leon3的源代码！(source code of leon3 )