该程序实现的是10进制的计数器，具有置位复位的功能。

说明：  用VHDL实现密码锁功能，用状态机实现，分管理员和用户两种功能，可分别修改密码，重置密码等。(codelock，VHDL，state)

matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

This rar files contains the presentation about FPGA and CPLD .

出租车自动计费系统的verilog程序代码(Taxi automated billing system verilog code)

利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP

在汉明码调试中实现了纠错原理，达到更快的效果，更少的资源浪费

用verilog写的cpld的各种分频程序，希望大家指正，谢谢！-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!

《可综合的Verilog语法》国外著名大学老师编写，对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.

RS232接收程序 无奇偶校验位 并行输出8位数据与data_ready数据准备好信号(RS232 receive procedures without parity 8-bit parallel output data and data ready signal data_ready)

generate sine wave. Inputs : Amplitude, phasein, frequency