该程序实现的是10进制的计数器，具有置位复位的功能。

spi-slave通信的vhdl实现及其仿真(VHDL implementation of spi-slave communication)

模拟地铁自动售票机选票、付款、取票、找零等功能，包含软件仿真和硬件响应，可供仿真测试和FPGA验证。(Analog subway ticket vending machine ballots, payment, tickets, give change and other features, including software simulation and hardware response for simulation and FPGA verification test.)

parity encoder test bench

VHDL语言实现的16位快速乘法器-VHDL of 16 rapid Multiplier

sigmoid函数硬件实现，verilog代码及其测试用例(Sigmoid function hardware implementation, verilog code and test cases)

实现verilog16位乘法器，verilog新手(achieve 16-bit multiplier)

基于FPGA的1553b接口设计详细设计论文(1553B design based on FPGA)

Verilog-RISC CPU

BT656转RGB的算法实现代码，使用VORILOG语言编写(BT656-->RGB, verilog)

说明：  i2c module，有i2c主机和从机模块(i2c module verilog VHDL base on i2c protocol)