这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！...

编程规范是重中之重，带你书写良好的变成习惯(It is used to measure noise and detect road noise pollution. It is accurate and has good effect.)

结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source

E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw

对用开发板上开关产生的信息做汉明编码并通过串口发送至电脑(The Hamming code is generated from the switch on the development board and sent to the computer through the serial port.)

使用VHDL实现锁相环,是个学习VHDL的好例子,与众分享-PLL using VHDL, VHDL is learning a good example, sharing with the public

VHDL黄金版，本人费了九牛才找到，帮助初学者入门-VHDL version, I spent nine cattle to find help beginners entry

本科毕业设计，简易逻辑分析仪，重点在于用CPLD搭建显卡，输出VGA信号驱动显示器显示逻辑波形(A design for LA,use cpld to generate VGA signals.)

verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,

vhdl 实验报告 verilog rs触发器 vhdl实验 vhdl 实验 报告 verilog rs触发器 vhdl实验-Experimental report VHDL VHDL verilog rs flip-flop experiment experimental report VHDL VHDL verilog rs flip-flop experiment

基于Xilinx Spartan6的 一个简单的CPU MU0 VHDL(Based on a simple CPU Xilinx Spartan6 of MU0 VHDL)