这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！...

几个fpga竞赛的设计例-Several Example FPGA design contest

高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog

我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。 希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3-8 function decoder and testbench, 16 Register and testbench and traffic lights. Hopes to be able to discuss other beginners learning, and with the guidance of the master

与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。(I2C-Master Core)

xc3s400芯片详细的英文资料，xc3s400的FPGA开发板使用者必看-chip xc3s400 detailed information in English, xc3s400 the FPGA development board users see

存储示波器，功能齐全通过验证，毕业设计用-Storage oscilloscope, a full-featured validated, graduation design

processor design istruction load pipeline ,hazard

10G高速以太网mac VERILOG源码 可仿真可实现(10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation)

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)

可以实现2PSK的信号调制，已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)