vhdl 实验报告 verilog rs触发器 vhdl实验 vhdl 实验 报告 verilog rs触发器 vhdl实验...

包括Cyclone II EP2C20 原理图.CycloneII开发板原理图fpga.EP1C3T144 FPGA develop board manual.EP1C6Q240C6开发板原理图.EP2C8开发板原理图.EPM1270F256C5 MAX_II_board_schematics.SF-EP1V2+FPGA开发板原理图.XC3S400红色飓风开发板原理图.红色飓风II代开发板原理图2.(Including the Cyclone II EP2C20 schematic . CycloneII development board schematics fpga.EP1C3T144FPGA develop board manual.EP1C6Q240C6 development board schematic . EP2C8development board schematics . EPM1270F256C5MAX_II_board_schematics.SF-EP1V2+FPGA development board schematic . XC3S400red hurricane development board schematics. Red hurricane II development board schematic diagram2)

10进制计数器，VHDL描述的，实验必备-10 hexadecimal counters, VHDL description of the experiment must

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高级verilog编程实现讲义，全英文讲义 -Senior verilog programming lecture notes, handouts in English

Matlab - to hdl code for square root

costas载波恢复算法 锁相环路，注释很清楚(costas carrier recovery algorithm PLL)

It is a example about LCD by VHDL code

使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。和上一个文件razzle差不多，但是产生的效果不一样。-use of the VHDL language ALTERA company"s board up3 have vga signal containing a detailed analysis and explanation is a good guide. And on a razzle almost document, but the effects are not the same.

此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP

说明：  对于一串二进制数前置零的计数的Verilog程序(For a string of binary zero count Verilog pre-procedure)