XILINXCPLD combine the simulation RS232 communication Verilog source

采用VHDL语言设计的基于LUT的正弦波发生器，已通过调试，并给出了pics仿真结果

VCS详细学习资料。内涵专业研究院所内部培训资料。适合于初学者学习使用，易于上手。(VCS learning)

Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM

说明：  基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.(Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the button to switch the modulation of 25 , 50 , 75 and short press button to switch the modulation signal frequency 1k, 1.5k, 2k, 2.5k.)

verilog实现RTC功能，可直接用于芯片开发中。(verilog achieve RTC function can be directly used for chip development.)

LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL

六十进制计数器，显示0到60.可以用数码管显示。(Six decimal counter 0-60 can use the digital display.)

说明：  基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)

汉明码转换，在FPGA上用verilog实现(hamming encoder, using FPGA)

说明：  分数时延FIR滤波器FPGA设计的相关资料及软件无线电实验平台MFSS6842使用说明(Fractional delay FIR filter FPGA design related information and software radio experimental platform MFSS6842 instructions)