rs coding vvhdl I do not want to be able to know the specific useful whether you...

de2开发板上的一个小程序 模60的计数器/分频器(de2 board developed a small program module 60 of the counter/divider)

4位MCU AM2901的完整VHDL程序，AM2901为主程序，其他为实体库-4 MCU AM2901 complete VHDL program, AM2901-based procedures, other entities, the Treasury

能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写(can complete read or write sdram， only include Verilog code and no simulation files)

C++获取CPU占用率，一个类和一个头文件(Gets the CPU Use rate)

文章论述如何将向modelsim中添加仿真库，包括添加xilinx,altera,actel公司的仿真库的方法-Article on how to add ModelSim simulation library, including the add xilinx, altera, actel the company

数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms

cic_dec_8_three CIC 文件的ＶＨＤＬ-cic_dec_8_threeCIC documents VHDL

RS码的FPGA编码文件，QUARTUS工程(The RS codes FPGA encoded file, QUARTUS engineering)

采用Verilog HDL硬件语言设计,实现基本的公用电话计费功能,设计完整.-Using Verilog HDL language hardware design, the realization of the basic public telephone billing function, design integrity.

说明：  lab report for lab 4