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Image-Compress-FPGA_DSP
比较详细的阐述了图像压缩的原理,并基于DSP和VHDL实现该系统,最后在FPGA上通过.(More detailed exposition of the principles of image compress, and VHDL-based implementation of the system, and finally in the FPGA.)
- 2013-11-13 15:17:01下载
- 积分:1
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aes
Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.
- 2009-12-20 14:16:40下载
- 积分:1
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SinGen
使用Verilog编写的正弦波生成工程,使用ROM核产生,利用mif文件(Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file)
- 2015-04-24 16:40:21下载
- 积分:1
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JTAG
边界扫描技术相关资料,含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)
- 2016-02-24 19:10:03下载
- 积分:1
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math_real
in this code very useful for designing real number concept
- 2013-11-19 19:54:40下载
- 积分:1
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FPGA
基于FPGA的图像采集卡的设计与相关说明-FPGA-based design of frame grabbers and related note
- 2023-06-09 09:00:04下载
- 积分:1
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hapf
单相混合有源电力滤波器的设计与控制,在matlab中的仿真模型,功能效果很好。(The design and control of single-phase hybrid active power filter in matlab simulation model, the function works well.)
- 2012-12-11 16:17:23下载
- 积分:1
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fir_lms
基于FIR滤波器的LMS自适应算法的FPGA实现,verilog语言(FIR filter based on LMS adaptive algorithm on FPGA, VHDL language)
- 2015-10-11 19:23:03下载
- 积分:1
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实现在屏幕上显示绿色和红色相间的水平条纹
实现在屏幕上显示绿色和红色相间的水平条纹。其中,vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)
- 2020-06-24 02:00:02下载
- 积分:1
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基于FPGA的交通控制器
设计一个由一条主干道和一条支干道的汇合点形成的十字交叉路口的交通灯控制器: 1) 主、支干道各设有3个方向的绿、黄、红指示灯(左转、直行和右转),每个行驶方向均配有时间显示数码管;2) 主干道处于常允许通行状态,而支干道有车来才允许通行(由外部信号通知)。3) 当主、支道均有车时,两者交替允许通行,主干道每次放行90s,支干道每次放行60s,在每次由亮绿灯变成亮红灯的转换过程中,要亮5s黄灯作为过渡,并进行减计时显示。
- 2022-02-26 08:00:04下载
- 积分:1