vhdl coding for Carry Select Adder

Basic VHDL code to create a sine wave generator for an FPGA board.

说明：  通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集原码 开发软件 Quartus II -ATEREAL EPM1270T144C5N CPLD-based pressure sensor data acquisition source Quartus II development software

vhdl code for alu and detemines the basic components of alu unit in cpu system

JOP的RAM VHDL源码，经典的经典，不易找到的好东东，-JOP of RAM VHDL source code, classic classics, difficult to find a good price.

使用uaf42设计的有源滤波器，高通滤波器的设计参数记录(Using uaf42 design active filters, high-pass filter design parameters recorded)

基于 verilog的卷积运算代码，应用于离散小波分析。(verilog conv)

说明：  该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。(This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help document.)

加法器，输入两个整数，用电路图形式将其逻辑原理呈现出来，该加法器为8位运算，每一位都对应一张电路图，可展示其完整过程(Adder, input two integer, with circuit diagram form its logical principle appear, this adder is 8 bit arithmetic, each corresponding to a circuit diagram, can show the complete process)

说明：  credit base network on chip(network on chip (noc))