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简单的键盘接口模块程序
一个简单的键盘接口模块程序,对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
- 2020-06-24 02:00:02下载
- 积分:1
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Verilog代码支持IO中断的CPU实现
Verilog代码,支持IO,中断的cpu实现。(Verilog code, support IO, interrupt cpu implementation.)
- 2020-07-05 20:28:59下载
- 积分:1
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一些简单的VHDL实例,主要是介绍一些基本逻辑们及一些组合、时序电路的例子,供大家参考...
一些简单的VHDL实例,主要是介绍一些基本逻辑们及一些组合、时序电路的例子,供大家参考-Some simple examples of VHDL, mainly to introduce some basic logic and some combination of sequential circuit examples for your reference
- 2022-01-31 04:35:55下载
- 积分:1
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Verilog语法
Verilog语法教程,适合初学者,详细(Verilog instruction book)
- 2019-05-04 16:07:18下载
- 积分:1
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Slave-FIFO
详细讲解Slave FIFO模式下的初始化设置和相对应寄存器说明(Explain in detail the initial setup Slave FIFO mode and the corresponding register description)
- 2014-03-18 17:33:23下载
- 积分:1
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8b10b
8b10b编解码,用于光通信和千兆以太网,verilog编写,已验证(8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified)
- 2021-01-27 09:48:41下载
- 积分:1
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Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。...
Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis
- 2022-03-21 18:04:20下载
- 积分:1
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pci_fpga
对pci9054芯片的配置进行了设置,并对PCI9054的各状态机进行了设置,程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)
- 2013-10-12 11:39:45下载
- 积分:1
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led1
点亮led流水灯,通过调用锁相环,可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)
- 2020-06-16 07:00:01下载
- 积分:1
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用VHDL实现十六位移位乘法器 才有移位相加法来实现
用VHDL实现十六位移位乘法器 才有移位相加法来实现-Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
- 2022-04-17 17:23:11下载
- 积分:1