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使用FPGA透过RS232与PC的作沟通,
使用FPGA透过RS232与PC的作沟通,
- 2022-06-19 12:31:04下载
- 积分:1
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uart
用veriolg 语言编写的串口通讯程序,通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )
- 2010-08-16 10:41:03下载
- 积分:1
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Endat_2
Endat slave interface
- 2021-04-21 19:38:49下载
- 积分:1
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非常优秀的国外VHDL设计教程,可进行MODELSIM模拟等操作
非常优秀的国外VHDL设计教程,可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation
- 2023-05-15 08:55:03下载
- 积分:1
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82 VHDL, verilog test case, involving a variety of grammatical rules. which is...
包括VHDL、verilog在内的各种设计实例,是学习硬件描述语言的帮手。共有82个实验例子,涉及各种语法规则。-82 VHDL, verilog test case, involving a variety of grammatical rules. which is you learn the HDL language helper.
- 2023-06-06 10:15:04下载
- 积分:1
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VHDLexamples
这里面有很多的vhdl的编程的源代码,文件是全英文的,例子丰富(That there are a lot of vhdl programming source code, documentation is in English, and examples of rich)
- 2010-07-13 11:00:53下载
- 积分:1
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CircuitDesignwithVHDL[1]
这主要是学习vhdl和fpga设计的一些资料(study for vhdl and fpga)
- 2009-05-13 09:31:26下载
- 积分:1
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sobel
由Verilog编写在FPGA实现sobel算法应用于图像边缘检测,工程文件可在quartus13.1以上版本打开;工程使用到ram、fifo、pll三种ip核,design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块,sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果;测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化,再将生成文件中数据用串口发给FPGA,边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
- 2021-01-15 21:08:46下载
- 积分:1
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pinlvji
verilog 简易频率计的设置,包括整个工程(verilog simple frequency meter settings, including the entire project)
- 2013-08-18 09:53:52下载
- 积分:1
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QPSK
In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.
- 2014-11-19 04:27:20下载
- 积分:1