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一个使用VHDL设计的具有强大功能的32位CPU,这个文件包含了与之配套的DDR控制器程序!...
一个使用VHDL设计的具有强大功能的32位CPU,这个文件包含了与之配套的DDR控制器程序!-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
- 2023-08-19 21:45:03下载
- 积分:1
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iic
iic 总线 verilog 源代码
标准i2c总线, 有sda scl 时钟,频率自定(IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-)
- 2007-10-24 17:52:33下载
- 积分:1
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top
说明: FPGA程序的top.v文件,主要实现DDS信号发生器功能,通过定时器,可简单实现输出幅值无极跳变(FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping)
- 2008-12-05 16:18:28下载
- 积分:1
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Writing Testbenches using System Verilog
Material to learn how to use system verilog and how to write testbenches for verification.
- 2018-02-09 17:24:25下载
- 积分:1
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DDS-Basic-principle
DDS基本原理,详细讲述了DDS基本原理及设计技巧(DDS Basic principle)
- 2015-09-14 21:38:26下载
- 积分:1
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uart_tx
FPGA UART 发送端程序 verilog语言编写
9600波特率 实用(UART transmit side program verilog language 9600 baud)
- 2013-08-14 16:33:34下载
- 积分:1
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single_phase_inverter_wangyafankui
带有电网电压反馈的单相PWM整流器反馈,输出的波形很好,适合初学者学习观摩(With power grid voltage feedback single-phase PWM rectifier feedback, the output waveform is very good, suitable for beginners learning view
)
- 2012-11-30 16:16:04下载
- 积分:1
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A4_Uart_Top
串口! 这是一个使用的通信程序 , 非常好用。(serial port Serial port! This is a communication program used, very useful.)
- 2020-06-17 14:00:01下载
- 积分:1
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使用Veriolog hdl 编写手机屏测试程序.
使用Veriolog hdl 编写手机屏测试程序.-Veriolog hdl prepared to use cell phone screen test.
- 2023-04-25 00:20:03下载
- 积分:1
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系统设计
说明: 基于数码管独立显示和三色灯的交通指示系统设计(Design of Traffic Indicator System Based on Digital Tube Independent Display and Tri-color Lamp)
- 2020-06-21 02:00:01下载
- 积分:1