Detailed description of the FPGA design flow of the entire FPGA design flow full...

说明：  Xilinx原语的使用介绍，特别全面，希望对大家有所帮助，(Introduction to the use of Xilinx primitives, particularly comprehensive,I hope it will be helpful to you all.)

说明：  基于FPGA的Veilog HDL实现代码，简单明了，希望能帮助verilog的初学者……(ＤＤＳ　based on Verilog ＤＨＬ for FPGA　)

verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。(verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.)

verilog开发FPGA，实现RS485串口通信(RS485 driver for FPGA )

同步fifo的调用程序，调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)

这是使用VHDL编写的交通灯程序,供大家交流学习-This is the use of VHDL prepared by the traffic lights procedures for the exchange of learning

Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl

基于vhdl的dds任意函数发生器的实现和仿真

LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL

verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)