VHDL硬件描述语言作业

xilinx accel dsp实例项目工程-xilinx accel dsp project

无线通信FPGA实现的代码 有matlab和verilog(FPGA implementation of wireless communication code matlab and verilog)

Generating a wider ALU from two small ones

说明：  BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim

VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)

改程序将实现对两个信号的曼切斯特编码，以用仿真软件验证过了(Reform program will achieve two Manchester encoded signal to a validated using simulation software)

4*4键盘设计，能运行，是我自己编译的，是初学者的工具(4* 4 keyboard design, can run my own compilation, is a tool for beginners)

卷积码（213）的编译码，VHDL语言编写的整个工程文件，带有仿真结果图。(Convolution code (213) codec, VHDL language of the whole project file with the simulation results shown in Fig.)