VHDL硬件描述语言作业

用Verilog语言编写的产生正弦波和方波的程序(Generate sine and square wave Verilog language program)

QPSK调制，QPSK仿真误码率,QPSK理论误码率 , QPSK仿真误比特率 , QPSK理论误比特率 (QPSK modulation, the signal-to-noise ratio)

自己去年做的实训项目，基于FPGA的VHDL的电子琴，可实现自动演奏与手动演奏，手动演奏是用PS2键盘听过按键来实现电子琴的发音，并且用VGA显示音符与音键，本设计采用模块化设计，底层使用代码，通过例化成原理图，最终在底层实现原理图之间的连接。

vhdl,十进制加减计数器，输出计数序列信号-vhdl, decimal addition and subtraction counter, the output count sequence signal

说明：  quartus 的一个实例,希望对刚刚学习quartus 的人有点帮助(Quartus an example, in the hope that people just learning a little help Quartus)

基于FPGA的Spartan-6系列的SOBEL算法实现(Implementation of SOBEL Algorithm Based on FPGA)

The project is used to perform the operation of 4 bit arethmatic and logical operation. the projcet is implemented in spartan 3E

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

SPI串行总线接口的Verilog实现，详细讲解实现过程。-SPI serial bus interface Verilog realization elaborate on the realization of the process.

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))