一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码

8051core-Verilog FPGA

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)

时钟在单片机中的应用，用于控制中断及显示程序(Clock in the MCU application, used to control interrupt and display program)

to learn bout development of vhdl code

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)

用verilog HDL编写的SPI控制器，从国外网站上找到的。-SPI (Serial Peripheral Interface) is serial, synchronous, full duplex communication protocol. It is widely used as a board-level interface between different devices such as microcontrollers, DACs, ADCs and others.

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序-Using VHDL realize CPLD (EPM240T100C5) the serial receive procedure

基于Verilog的图像采集、处理和存储程序，初学者参考，高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)

说明：  I2C 从设备通讯应用示范程序，用于I2C设计验证(I2C slave communication application demo program, used to for I2C design verification )

verilog file , FPGA controll vga display- verilog file , FPGA controll vga display