USB245I based FPGA VHDL of the driver, should useful

VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是51~94个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC publication, here is the 51 ~ 94 examples

资源描述这个秒表特点是计数到59分59秒9，并且有可以让计数暂停和清零。采用了二分频，六进制和十进制组合，加上扫描电路设计而成的。

ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.

RGB 与YCbCr 颜色空间可以相互转化(RGB and YCbCr color space can be transformed into each other)

基于FPGA的多电平载波移相SPWM方法实现(theCarried-Phase-shift SPWM method of Multi-Level converter based on FPGA)

QuartusII多路选择器,数字电路环境，大三EDA技术实验(Quartus,chosen conductos in matheathics field)

Vhdl 语言在 pdf 格式的波斯语。你可以学习编码用 vhdl 语言、 fpga、 盖茨、 专用集成电路、 cpu 编程，在 2 个部分。

VHDL数字系统设计和工程实践3，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, 3, including the principles, truth table and schematic, as well as VHDL source code.

如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。 模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。 (As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)

program for half subtractor.