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ROM建立平方电路
A ROM to build a squaring circuit
- 2022-08-07 16:45:22下载
- 积分:1
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基于vhdl的dds设计
基于vhdl的dds任意函数发生器的实现和仿真
- 2022-12-25 16:15:09下载
- 积分:1
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对16×16次VHDL实例,如果需要详细的请让我知道
VHDL examples for 16x16 times, if need detail pls let me know
- 2022-04-08 01:26:55下载
- 积分:1
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STM32与FPGA通信
stm32与fpga之间的通信,协议是SPI的,可双向通信(双向通信需要自己例化,只例化了fpga到stm32)(Communication between STM32 and FPGA, the protocol is SPI, two-way communication (two-way communication needs to be taken as an example, only FPGA to STM32))
- 2020-11-16 09:49:40下载
- 积分:1
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Cadence-Allegro-PCB-SI
利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)
- 2013-08-06 22:17:46下载
- 积分:1
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2010_5
PI控制器的算法及源码,迅速掌握FPGA的VHDL算法实现!(Algorithm and source code of PI controller, quickly grasp the implementation of VHDL algorithm in FPGA!)
- 2014-07-04 15:25:59下载
- 积分:1
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High-speed-digital-correlator
16位高速数字相关器的VERIOLOG程序,已经编译通过了,可以使用(16-bit high-speed digital correlator VERIOLOG program has been compiled by, you can use)
- 2020-10-09 11:37:34下载
- 积分:1
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EX12
说明: 这是一个用Verilog语言编写的一组程序,主要是熟悉开发板的应用,以及verilog语言(This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language)
- 2011-03-03 09:38:38下载
- 积分:1
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cnt
在ise开发环境下,建立顶层模块和子模块的层次结构,其实现的功能是一个可复位课暂停开始继续的建议秒表(In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch)
- 2014-11-03 19:35:21下载
- 积分:1
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modelsim_example_c
modelsim仿真,大量vhdl程序,验证,很有价值!(The ModelSim Simulation, a large number of VHDL procedures, validation, great value!)
- 2013-05-05 15:11:06下载
- 积分:1